The present invention is directed to methods for estimating cell delay and net delay for an integrated circuit design. More specifically, but without limitation thereto, the present invention is directed to modeling the resistance and capacitance variation as functions of physical parameters to calculate an estimated cell delay and net delay for an integrated circuit design.
Process variations in the manufacture of integrated circuits result in corresponding variations in the cell delay and net delay that must be accounted for in timing calculations for the integrated circuit design. In previous methods, the best and worst case variations are used to calculate the minimum and maximum cell and net delays. These methods are collectively referred to as corner SPEF (standard parasitic exchange format). Some of these methods include calculations for variations that lie between the extremes to cover all the variation effects. Disadvantageously, at least two extraction steps are required to calculate the delays for each variation considered. Also, for each variation, a technology file containing capacitance information for specific wire line configurations must also be generated for the extraction tool. Moreover, the physical conditions that result in worst case delay depend on the net, even to the extent that the worst case conditions for a high drive cell can be the best case conditions for a lower drive cell. Another disadvantage of corner SPEF methods arises in timing checks. A timing check determines whether the setup and hold time is met for each flip-flop in the integrated circuit design. In the worst case, the check is made with a fast clock versus slow data. However, the corner SPEF methods provide a slow clock and slow data, which is not conservative enough for a zero cycle path (the input to the first set of flip-flops) and a path without a well balanced clock tree. In other words, the corner SPEF methods do not separate the clock net and the data net.